Performance evaluation of 64-Bit MAC Unitsusing Different Multipliers In Terms of Area, Power Dissipation and Delay

Abstract

64-bit multiplier-and-accumulator unit is designed using different type of multipliers such as Array Multiplier, Wallace-tree Multiplier, Booth Multiplier and Vedic Multiplier. Implementation of design is programmed using Verilog coding and design synthesis is performed using Encounter RTL compiler-Cadence. Evaluating the performance of various multipliers is performed in terms of area, power dissipation and speed.The best multiplier is one that has high speed capacity, low power consumption and low power dissipation. Once implementation of MAC unit is done using all different multipliers, analysis of area, power and speed is done on Cadence tool. On the comparison of all the above mentioned parameter, a conclusion is made that Vedic multiplier has comparatively good performance among all multipliers.