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Abstract
In this paper, AHB AMBA system and its hardware implementation is described. The main objective of this paper is to learn AMBA (AHB and APB) protocol and develop sub-modules. The paper provides information regarding 4-beat incrementing burst, locked and split transfers. The AHB consists of AHB masters which has separate instruction and data memory and AHB driven output logic to interface with AHB Bus. The interface between AMBA bus High Performance & Low performance is designed to drive read / write memory slave. The system consists of three Masters, Decoder, and Master to Slave Multiplexer, Slave to Master Multiplexer, Arbiter, APB Bridge and three Slaves. Each master has its own slave which drives it through address, control and data bus when granted by arbiter. The arbiter allows only one bus master to drive various buses namely the data, address and control bus. The design is a 32-bit AHB master which performs load and store to slave’s memory, AHB and APB bus to interface masters and slaves. The design is simulated and synthesis in XILINX.