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Abstract
The importance of reversible logic is increasing day by day and beseeming more salient logic in terms of optimized delay and power based output and has been integrated into a number of applications these days such as Low Power VLSI, DNA Computing, Bio Informatics and many more. Earlier, the major reason of power dissipation was used to be the loss of bits of information i.e. The garbage bits during the procedure of logical operations, but this problem can be minimized accompanying reversible gates as it involves one –to – one mapping of input and output vectors which results in reduction of garbage bits. Along with that, as the full adder is the essential part in most of the digital computerised logics, so the comparison between different reversible gates based 1 bit full adder to find out the most efficient circuits with respect to, LP (Leakage Power), DP (Dynamic Power),Area and Delay (Worst Path) is presented in this paper. The RTL examination was completed utilizing Cadence Tool for Area, Delay and Power at 45 nanometre and 90 nanometre innovation for both slow and fast libraries.