Comparative Performance Analysis of Low Offset High Speed CMOS Voltage Comparator

Abstract

This paper presents comparative performance analysis of Low Offset High Speed Voltage Comparators. High speed applications and technology is becoming an increasingly important and growing area of electronics. Various types of dynamic latch comparators which include resistive dividing comparator; current sensing comparator; charge sharing comparator and modified high speed CMOS Voltage Comparator simulated for the different characteristics in generic 90 nm CMOS Technology. In modified comparator design an attempt has been made to reduce the offset error generated within the latched comparator by introducing Offset Reduction Block.