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Abstract

This paper presents the design and analysis of Pure Double Tail Comparator & Pure Dynamic Comparator. The enhancement in energy in Power dissipation, and Delay is one of the major challenging issues in the field of VLSI design model. Therefore, the use of adiabatic logic offer significant Power Dissipation and Delay problem as compare to Pure Double Tail Comparator and Pure Dynamic Comparator. The Double Tail Comparator has been design with adiabatic logic and it is simulated. Partially adiabatic Logic design technique is used in this paper . Analysis is done on the basic of performance parameters, which are compared in the terms of  Power Dissipation, and Delay. In this paper, we analyze the performance of Pure Double Tail Comparator (P-DTC) using with Adiabatic Double Tail Comparator (A-DTC) with the variation of frequency (GHz) and temperature (Degree Celsius). Simulation  results reveals that the A-DTC is comparatively 90% more power efficient than Pull up and pull down network base design. Further, it also reduces the delay time.

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